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| CXP740000 CMOS 8-bit Single Chip Microcomputer Description The CXP740000 is a CMOS 8-bit single chip microcomputer of piggyback/evaluator combined type, which is developed for evaluating the function of the CXP740056/740096/740010. Piggy/evaluation chip 100 pin PQFP (Ceramic) Features * A wide instruction set (211 instructions) which LQFP supported QFP supported covers various types of data. --16-bit operation/multiplication and division/ Boolean bit operation instructions * Minimum instruction cycle 167ns at 24MHz operation (4.5 to 5.5V) 333ns at 12MHz operation (2.7 to 5.5V) 122s at 32kHz operation (2.7 to 5.5V) * Applicable EPROM CXP27C702K (Maximum 120K bytes are available.) * Incorporated RAM capacity 4096 bytes * Peripheral functions -- A/D converter 8 bits, 8 channels, successive approximation method (Conversion time of 10.3s/24MHz) -- Serial interface Start-stop sync type (UART), 1 channel Incorporated buffer RAM (Auto transfer for 1 to 32 bytes), 2 channels 8-bit clock sync type (MSB/LSB first selectable), 1 channel -- Timer 8-bit timer, 2 channels 8-bit timer/counter, 2 chennels 19-bit time-base timer, 16-bit capture timer/counter 32kHz timer/counter -- Remote control unit receive circuit Internal noise elimination circuit Internal 8-bit, 6-stage FIFO for measured data -- PWM output 12 bits, 12 channels * Interruption 24 factors, 15 vectors, multi-interruption possible * Standby mode Sleep/stop * Package 100-pin ceramic PQFP Note) Mask option depends on the type of the CXP740000. Refer to the Products List for details. Structure Silicon gate CMOS IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E98429-PS CXP740000 Pin Assignment in Piggyback Mode (QFP package) PI3/TO0/ADJ PI4/INT1/CS1 PK2/TEX PI1/RMC PC7 PA0 PA3 PA5 PA2 PA7 VDD 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 PC5 PC4 PC3 PC2 PC1 PC0 PB7/SI2 PB6/SO2 PB5/SCK2 PB4/TO2 PB3 PB2 PB1 PB0 PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 1 2 3 4 5 6 7 80 79 78 77 76 75 74 PI6/SO1 PI7/SI1 PE0/INT0 PE1/INT2 PE2/PWM0 PE3/PWM1 PE4 PE5 PE6 PE7 PG0/TxD PG1/RxD PG2/EC0 PG3/EC1 PG4/EC2 PG5/INT3 PG6/INT4 PG7/CINT AN0 AN1 AN2 AN3 PF0/AN4 PF1/AN5 PF2/AN6 PF3/AN7 AVDD AVREF AVSS PF4/AN8 NC A12 A15 A14 A13 VDD PK1/TX PI2/NMI PC6 PA1 PA4 PA6 PI5/SCK1 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 9 10 11 12 13 14 15 16 17 18 19 20 21 4 A6 A5 A4 A3 A2 A1 A0 NC D0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 3 2 1 32 31 30 29 28 27 26 25 24 23 22 21 A8 A9 A11 NC OE A10 CE D7 D6 D1 D2 GND D3 D4 XTAL 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PH7 PH4 A16 D5 22 A7 8 NC VSS PF7/AN11 PF6/AN10 PH2 PH0 PK6/CS0 PK5/SI0 PH5 PK4/SO0 EXTAL PH6 RST PH3 PH1 VSS Note) 1. NC (Pin 90) is left open. 2. VSS (Pins 41 and 88) are both connected to GND. -2- PK3/SCK0 PK7/TO1 PF5/AN9 CXP740000 Pin Assignment in Piggyback Mode (LQFP package) PI3/TO0/ADJ PI4/INT1/CS1 PI5/SCK1 PK2/TEX PI1/RMC PK1/TX PI6/SO1 PC7 PA3 PA5 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 NC D0 D1 D2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 VDD A14 A13 A8 A9 A11 OE A10 CE D7 D6 D5 D4 D3 A16 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PE1/INT2 PE2/PWM0 PE3/PWM1 PE4 PE5 PE6 PE7 PG0/TxD PG1/RxD PG2/EC0 PG3/EC1 PG4/EC2 PG5/INT3 PG6/INT4 PG7/CINT AN0 AN1 AN2 AN3 PF0/AN4 PF1/AN5 PF2/AN6 PF3/AN7 AVDD AVREF PC3 PC2 PC1 PC0 PB7/SI2 PB6/SO2 PB5/SCK2 PB4/TO2 PB3 PB2 PB1 PB0 PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 PD7 PD6 PD5 PD4 PD3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VSS NC PI7/SI1 PF4/AN8 PC4 PC5 PA1 PA0 PA7 VDD PK7/TO1 EXTAL PK3/SCK0 Note) 1. NC (Pin 88) is left open. 2. VSS (Pins 39 and 86) are both connected to GND. -3- PF7/AN11 PF6/AN10 PK6/CS0 PK4/SO0 PF5/AN9 XTAL PK5/SI0 AVSS PH7 PD0 PH4 PH3 PH0 RST PD1 PH5 PH1 PD2 PH6 PH2 VSS PE0/INT0 PA2 PA4 PA6 PI2/NMI PC6 CXP740000 Pin Assignment in Evaluator Mode (QFP package) PI4/INT1/CS1 PI3/TO0/ADJ PK2/TEX PI1/RMC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 PC5 PC4 PC3 PC2 PC1 PC0 PB7/SI2 PB6/SO2 PB5/SCK2 PB4/TO2 PB3 PB2 PB1 PB0 PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 1 2 3 4 5 6 80 79 78 77 76 75 PI6/SO1 PI7/SI1 PE0/INT0 PE1/INT2 PE2/PWM0 PE3/PWM1 PE4 PE5 PE6 PE7 PG0/TxD PG1/RxD PG2/EC0 PG3/EC1 PG4/EC2 PG5/INT3 PG6/INT4 PG7/CINT AN0 AN1 AN2 AN3 PF0/AN4 PF1/AN5 PF2/AN6 PF3/AN7 AVDD AVREF AVSS PF4/AN8 PI2/NMI PC6 PA1 PA4 PA6 PI5/SCK1 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PC7 PA0 PA3 PA5 PA2 PA7 VDD A7/D7 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 A12 A15 4 A6/D6 A5/D5 A4/D4 A3/D3 A2/D2 A1/D1 A0/D0 NC RD 5 6 7 8 9 10 11 12 13 3 2 1 32 31 30 29 28 27 26 25 24 23 22 21 A8 A9 A11 NC HALT A10 E/P I/T MON 14 15 16 17 18 19 20 SYNC WR GND C2 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 RST A16 C1 22 A14 A13 NC VDD VSS NC PK1/TX PK4/SO0 EXTAL PH6 RST PH3 PH1 VSS PK3/SCK0 PK7/TO1 Note) 1. NC (Pin 90) is left open. 2. VSS (Pins 41 and 88) are both connected to GND. -4- PF7/AN11 PF6/AN10 PK6/CS0 PF5/AN9 PH4 XTAL PH7 PH2 PH0 PK5/SI0 PH5 CXP740000 Pin Assignment in Evaluator Mode (LQFP package) PI3/TO0/ADJ PI4/INT1/CS1 PI5/SCK1 PK2/TEX PI1/RMC PK1/TX PI6/SO1 PC7 PA3 PA5 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 A15 A12 A7/D7 A6/D6 A5/D5 A4/D4 A3/D3 A2/D2 A1/D1 A0/D0 NC RD WR SYNC GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 VDD A14 A13 A8 A9 A11 HALT A10 E/P I/T MON RST C1 C2 A16 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PE1/INT2 PE2/PWM0 PE3/PWM1 PE4 PE5 PE6 PE7 PG0/TxD PG1/RxD PG2/EC0 PG3/EC1 PG4/EC2 PG5/INT3 PG6/INT4 PG7/CINT AN0 AN1 AN2 AN3 PF0/AN4 PF1/AN5 PF2/AN6 PF3/AN7 AVDD AVREF PC3 PC2 PC1 PC0 PB7/SI2 PB6/SO2 PB5/SCK2 PB4/TO2 PB3 PB2 PB1 PB0 PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 PD7 PD6 PD5 PD4 PD3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PH5 PH1 VSS VSS NC PF7/AN11 PF6/AN10 PD2 PH6 PH2 PK6/CS0 PK4/SO0 PI7/SI1 PF4/AN8 PC4 PC5 PA1 PA0 PA7 VDD PK7/TO1 EXTAL Note) 1. NC (Pin 88) is left open. 2. VSS (Pins 39 and 86) are both connected to GND. -5- PK3/SCK0 PF5/AN9 XTAL PK5/SI0 AVSS PH7 PD0 PH4 PH3 PH0 RST PD1 PE0/INT0 PA2 PA4 PA6 PI2/NMI PC6 CXP740000 EPROM Read Timing (Ta = -20 to +75C, VDD = 2.7 to 5.5V, Vss = 0V reference) Item Address data input delay time Address data hold time Symbol Pin A0 to A15 D0 to D7 A0 to A15 D0 to D7 0 Min. Max. 1001 502 Unit ns ns tACC tIH 1 At 12MHz operation (VDD = 4.5 to 5.5V) 2 At 12MHz operation (VDD = 2.7 to 5.5V), at 24MHz operation (VDD = 4.5 to 5.5V) 0.8VDD A0 to A15 Address data 0.2VDD tACC tIH 0.8VDD Input data 0.2VDD D0 to D7 Products List Products Option item Mask ROM CXP740056 CXP740096 CXP740010 Package ROM capacity Pull-up resistor for reset pin 100-pin plastic QFP/LQFP 56K bytes 96K bytes 120K bytes Piggy/evaluation chip CXP740000-U01Q CXP740000-U01R 100-pin ceramic PQFP EPROM 120K bytes Existent Existent/Non-existent -6- CXP740000 Piggyback mode/evaluator mode can be switched as shown below. Piggyback mode Piggy/evaluation chip Evaluator mode Pin 1 marking LCC type EPROM Pin 1 marking Pin 1 index Note) CPU probe EPROM adaptor Pin 1 marking Note) Evaluation cap should be connected to CPU probe. Pin 1 index -7- CXP740000 Package Outline Unit: mm 100PIN PQFP (CERAMIC) PIN NO. 1 INDEX INDEX 100 18.7 16.3 0.2 81 81 100 PIN No. 1 INDEX 1 80 80 1 0.65 0.05 4.5 1.27 0.13 22.3 0.25 18.12 0.2 12.02 14.22 24.7 6.0 0.3 1.0 0.7 30 51 51 30 31 9.48 11.66 15.58 0.2 50 1.3 0.3 50 0.45 31 PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE PQFP-100C-L01 AQFP100-C-0000-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT CERAMIC GOLD PLATING 42 ALLOY 5.7g 3.57 0.36 JEDEC CODE + 0.05 0.15 - 0.02 100PIN PQFP(CERAMIC) 16.0 0.5 0.50 0.25 10.44 MAX 0.5 0.05 14.0 0.2 75 76 51 50 12.4 12.0 0.15 + 0.08 0.18 - 0.03 100 1 INDEX 25 26 1.5 3.2 0.2 0.8 0.1 INDEX 3.32 + 0.05 0.127 - 0.02 + 0.15 0.2 - 0.13 PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE PQFP-100C-L05 AQFP100-C-0000 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS CERAMIC GOLD PLATING 42 ALLOY 2.4g -8- 6.9 0.3 0.08 |
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